Transistor, meomory cell array and method of manufacturing a transistor

ABSTRACT

A transistor, memory cell array and method of manufacturing a transistor are disclosed. In one embodiment, the invention refers to a transistor, which is formed at least partially in a semiconductor substrate, comprising a first and a second source/drain regions, a channel region connecting said first and second source/drain regions, said channel region being disposed in said semiconductor substrate, and a gate electrode disposed along said channel region and being electrically isolated from said channel region, for controlling an electrical current flowing between said first and second source/drain regions, wherein said channel region comprises a fin-region in which the channel has the shape of a ridge, said ridge comprising a top side and two lateral sides in a cross section perpendicular to a line connecting said first and second source/drain regions, wherein said top side is disposed beneath a surface of said semiconductor substrate and said gate electrode is disposed along said top side and said two lateral sides.

FIELD OF THE INVENTION

The present invention relates to a transistor, a memory cell arraycomprising a plurality of memory cells incorporating the transistor, aswell as a method of manufacturing a transistor.

BACKGROUND

Memory cells of a dynamic random access memory (DRAM) comprise a storagecapacitor for storing an electrical charge which represents aninformation to be stored, and an access transistor for addressing thestorage capacitor. The access transistor comprises a first and a secondsource/drain regions, a conductive channel adjacent to the first andsecond source/drain regions as well as a gate electrode controlling anelectrical current flowing between the first and second source/drainregions. The transistor usually is formed in a semiconductor substrate.The information stored in the storage capacitor is read out or writtenin by addressing the access transistor. There is a lower boundary of thechannel length of the access transistor, below which the isolationproperties of the access transistor in an non-addressed state are notsufficient. The lower boundary of the effective channel length L_(eff)limits the scalability of planar transistor cells having an accesstransistor which is horizontally formed with respect to the substratesurface of the semiconductor substrate.

Vertical transistor cells offer a possibility of enhancing the channellength while maintaining the surface area necessary for forming thememory cell. In such a vertical transistor cell the source/drain regionsof the access transistor as well as the channel region are aligned in adirection perpendicular to the substrate surface. One of the problemsinvolved with such a vertical transistor cell is the difficulty inproviding a surface contact to a stacked capacitor. Accordingly, such avertical transistor is difficult to integrate with a stack capacitor.

A concept, in which the effective channel length L_(eff) is enhanced,refers to a recessed channel transistor, as is for example known fromU.S. Patent No. 5,945,707. In such a transistor, the first and secondsource/drain regions are arranged in a horizontal plane parallel to thesubstrate surface. The gate electrode is arranged in a recessed groove,which is disposed between the two source/drain regions of the transistorin the semiconductor substrate. Accordingly, the effective channellength equals to the sum of the distance between the two source/drainregions and the two fold of the depth of the recess groove. Theeffective channel width W_(eff) corresponds to the minimal structuralsize F.

Another known transistor concept refers to the FinFET. The active areaof a FinFET usually has the shape of a fin or a ridge which is formed inthe semiconductor substrate between the two source/drain regions. A gateelectrode encloses the fin at two or three sides thereof.

SUMMARY

Embodiments of the invention provide a transistor, a memory cell array,and a method of manufacturing a transistor. In one embodiment, theinvention provides a transistor, which is formed at least partially in asemiconductor substrate, comprising a first and a second source/drainregions, a channel region connecting said first and second source/drainregions, said channel region being disposed in said semiconductorsubstrate, and a gate electrode disposed along said channel region andbeing electrically isolated from said channel region, for controlling anelectrical current flowing between said first and second source/drainregions, wherein said channel region comprises a fin-region in which thechannel has the shape of a ridge, said ridge comprising a top side andtwo lateral sides in a cross section perpendicular to a line connectingsaid first and second source/drain regions, wherein said top side isdisposed beneath a surface of said semiconductor substrate and said gateelectrode is disposed along said top side and said two lateral sides.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the present invention and are incorporated in andconstitute a part of this specification. The drawings illustrate theembodiments of the present invention and together with the descriptionserve to explain the principles of the invention. Other embodiments ofthe present invention and many of the intended advantages of the presentinvention will be readily appreciated as they become better understoodby reference to the following detailed description. The elements of thedrawings are not necessarily to scale relative to each other. Likereference numerals designate corresponding similar parts.

FIGS. 1A to 1C illustrate exemplary embodiments of a transistor of thepresent invention.

FIGS. 2A to 2W illustrate one embodiment of a memory cell array of thepresent invention.

FIGS. 3A to 3L illustrate another embodiment of a memory cell array ofthe present invention.

FIGS. 4A to 4J illustrate another embodiment of a memory cell array ofthe present invention.

FIGS. 5A to 5K illustrate another embodiment of a memory cell array ofthe present invention.

DETAILED DESCRIPTION

In the following Detailed Description, reference is made to theaccompanying drawings, which form a part hereof, and in which isillustrated by way of illustration specific embodiments in which theinvention may be practiced. In this regard, directional terminology,such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc.,is used with reference to the orientation of the Figure(s) beingdescribed. Because components of embodiments of the present inventioncan be positioned in a number of different orientations, the directionalterminology is used for purposes of illustration and is in no waylimiting. It is to be understood that other embodiments may be utilizedand structural or logical changes may be made without departing from thescope of the present invention. The following detailed description,therefore, is not to be taken in a limiting sense, and the scope of thepresent invention is defined by the appended claims.

The present invention provides a transistor that eliminates the problemsinvolved with conventional transistors. The present invention provides amemory cell array as well as a method of manufacturing a transistor.

These and other needs are achieved by a transistor, especially for usein a DRAM cell, said transistor being formed at least partially in asemiconductor substrate, comprising a first source/drain region, a firstcontact region which is adapted to connect the first source/drain regionwith an electrode of a storage capacitor, a second source/drain region,a second contact region which is adapted to connect the secondsource/drain region with a bitline, a channel region connecting saidfirst and second source/drain regions, said channel region beingdisposed in said semiconductor substrate, and a gate electrode disposedalong said channel region and being electrically isolated from saidchannel region by a gate isolating layer, said gate electrodecontrolling an electrical current flowing between said first and secondsource/drain regions, wherein said channel region comprises a fin-regionin which said channel region has the shape of a fin and in which thegate electrode is disposed at three sides of the channel region, whereina current path connecting said first and second contact regionscomprises a first vertical region in which the direction of said currenthas a component in a first vertical direction, a horizontal region inwhich the direction of said current has a horizontal component, and asecond vertical region in which the direction of said current has acomponent in a second vertical direction, said first vertical directionbeing opposed to said second vertical direction.

Accordingly, the transistor of the present invention is implemented as aFinFET, having an active area with the shape of a ridge or a fin.Thereby, the conductive channel connecting first and second source/drainregions can be fully depleted, whereby an off-current of the transistoris reduced. In addition, since the current path additionally comprises avertical component, the off-current can further be reduced.

The present invention additionally provides a transistor, especially foruse in a DRAM cell, said transistor being formed at least partially in asemiconductor substrate, comprising a first source/drain region, asecond source/drain region, a channel region connecting said first andsecond source/drain regions, said channel region being disposed in saidsemiconductor substrate, a first direction being defined by a lineconnecting said first and second source/drain regions, and a gateelectrode disposed along said channel region and being electricallyisolated from said channel region by a gate isolating layer, said gateelectrode controlling an electrical current flowing between said firstand second source/drain regions, wherein said channel region comprises afin-region in which the channel has the shape of a fin, said fincomprising a top side and two lateral sides in a cross sectionperpendicular to said first direction, wherein said top side is disposedbeneath a surface of said semiconductor substrate and said gateelectrode is disposed along along said top side and said two lateralsides.

According to a preferred embodiment the distance between said top sideand said substrate surface, measured in a direction perpendicular tosaid substrate surface, is 10 to 200 nm. If the distance between the topside and the substrate surface is smaller than 10 nm the advantageouseffects of the present invention will be too weak. On the other hand, ifthe distance between the top side and the substrate surface is largerthan 200 nm, the channel length and, as a consequence, the channelresistance will remarkably be increased.

Moreover, the present invention provides a memory cell array comprisinga plurality of memory cells, a plurality of bitlines which are arrangedin a first direction and a plurality of wordlines which are arranged ina second direction intersecting said first direction, a memory cellcomprising a storage capacitor, a transistor, which is at leastpartially formed in a semiconductor substrate, said transistorcomprising a first source/drain region, a second source/drain region, achannel region connecting said first and second doped regions, saidchannel region being disposed in said semiconductor substrate and a gateelectrode disposed along said channel region and being electricallyisolated from said channel region, said gate electrode controlling anelectrical current flowing between said first and second source/drainregions, wherein said channel region comprises a fin-region in which thechannel has the shape of a fin, said fin comprising a top side and twolateral sides in a cross section perpendicular to a line connecting saidfirst and second source/drain regions, wherein said top side is disposedbeneath a surface of said semiconductor substrate and said gateelectrode is disposed along along said top side and said two lateralsides, wherein each of said wordlines is electrically connected with aplurality of gate electrodes, and wherein said second source/drainregion of each of said transistors is connected with one of saidbitlines via a bitline contact.

In addition, the present invention provides a method of manufacturing atransistor in a semiconductor substrate, comprising the steps ofproviding said semiconductor substrate, defining two isolation trenchesa surface of said semiconductor substrate, for laterally confining anactive area in which the transistor is to be formed, filling saidisolation trenches with an isolating material, providing a gateelectrode which is isolated from said active area by a gate isolatingmaterial, providing a first and a second source/drain regions, wherein aconductive channel is formed between said first and second source/drainregions, a first direction being defined by a line connecting said firstand second source/drain regions, wherein said step of providing a gateelectrode comprises the steps of defining a groove in said active area,said groove extending from said surface of said semiconductor substratein a direction perpendicular to said surface to a first depth,thereafter, defining a pocket in each said isolation trenches at aposition adjacent to said groove so that said two pockets will beconnected with said groove and said groove is disposed between said twopockets, said two pockets extending to a second depth larger than saidfirst depth, providing a gate isolating material at an interface betweensaid active area and said groove and at an interface between said activearea and said pockets, depositing a gate electrode material so as tofill said groove and said two pockets, partially removing said gateelectrode material so that said gate electrode material is removed fromthe portions outside said groove and said two pockets.

According to the present invention, since the step of providing a gateelectrode comprises the step of forming a groove in the active areathereby defining the recessed channel portion, it is possible to alignthe recessed channel with the gate electrode.

According to a preferred embodiment, the method further comprises thestep of thinning the active area at a portion between said first andsecond depths in a direction parallel to said substrate surface andperpendicular to said first direction.

Thereby, it is possible to locally thin the active area at the channelregion which will later be enclosed by the gate electrode, whilemaintaining the area of the active region outside the gate electroderegion. In particular, the width of the source/drain regions ismaintained. As a consequence, the junction contact area will not bethinned whereby a contact resistance is reduced.

According to another embodiment the two pockets are defined by wetetching. Accordingly, the two pockets can be formed in a self-alignedmanner since they will only be formed at the portion adjacent to thegroove portion of the gate electrode. In addition, in case the grooveportions are defined by wet etching, it is possible to implement themethod in such a manner that the passing wordlines of the memory cellarray will be at a position near the surface of the semiconductorsubstrate so that an influence of the passing wordlines on the adjacentactive area will be decreased.

According to another embodiment of the present invention, the step ofproviding a gate electrode comprises the steps of defining a pocket ineach of said isolation trenches, said two pockets extending to a seconddepth, thereafter, defining a groove in said active area at a positionadjacent to the position of said pockets, so that said groove isdisposed between said two pockets and is electrically connected withsaid two pockets, said groove extending from said surface of saidsemiconductor substrate in a direction perpendicular to said surface toa first depth, wherein said second depth is larger than said firstdepth, providing a gate isolating material at an interface between saidactive area and said groove and at an interface between said active areaand said pockets, depositing a gate electrode material so as to fillsaid groove and said two pockets, partially removing said gate electrodematerial so that said gate electrode material is removed from theportions outside said groove and said two pockets. In this case, it isespecially preferred that the pockets are formed parallel to each otherso as to make an alignment of the pockets and the groove portion of thegate electrode easier.

FIG. 1A illustrates a cross-sectional view of the transistor 16 along adirection connecting first and second source/drain regions 121, 122.

The transistor 16 comprises a first and a second source/drain regions121, 122 and a channel 14 connecting the first and second source/drainregions 121, 122. The conductivity of the channel is controlled by thegate electrode 85. The active area 12 has the shape of a fin or a ridgeand three sides of the fin are enclosed by the gate electrode.

The first and second source/drain regions 121, 122 are disposed in thesurface region of a semiconductor substrate 1. The gate electrode 85comprises a groove region 852 and two plate-like portions 851. Thegroove region of the gate electrode 85 is disposed in a groove etched inthe substrate surface 10. Accordingly, the top side of the active areais disposed at a deeper depth than the surface 10 of the semiconductorsubstrate. The plate-like portions extend in a plane which lies beforeand behind the depicted cross-section and therefore are illustrated withbroken lines. The lower part of the groove region 852 is electricallyisolated from the silicon material by the gate oxide layer 80. The firstand second source/drain regions 121, 122 are electrically isolated fromthe groove-portions 852 by the silicon nitride spacer 86. In addition,the sacrificial silicon oxide layer 181 is disposed between the siliconnitride spacer 86 and the first and second source/drain regions 121,122. The first contact region 93 is provided so as to electricallyconnect the first source/drain region 121 with the storage capacitor,and a second contact region 94 is provided so as to electrical connectthe second source/drain region with a bit line (not shown).

The detailed implementation of the first and second contact regions 93,94 will be described later with respect to the first to fourthembodiments of the present invention.

The gate electrode 85 usually is made from polysilicon. The first andsecond source/drain regions 121, 122 are implemented as lightly n⁻ dopedsilicon region and, consequently, exhibit an excellent electricalconductivity. Optionally, the first source/drain region 121 or bothsource/drain regions 121, 122 may additionally comprise a lightly dopedregion (not shown), which is disposed between the channel region and thehighly doped regions, respectively. The channel 14 is lightly p⁻ dopedand therefore isolates the first from the second source/drain regionsunless a suitable voltage is applied to the gate electrode 52.

A current path between the first and the second contact regions 93, 94first extends in a first vertical direction, i.e., downwards, thereafterin a horizontal direction, and then upwards that is in a second verticaldirection which is opposite to the first vertical direction. Differentlystated, the current path comprises the channel region 14 as well as thedistance from the boundary of the source/drain region 121 to the contactregion 93, 94.

Accordingly, a current flowing from the first to the second contactregion 93, 94, will first have a weakly gated vertical path, thereafter,a strongly gated vertical path, followed by a strongly gated horizontalpath, a strongly gated vertical path and, thereafter, a weakly gatedvertical path. Differently stated, since the current path comprises aportion extending in a recess which is formed in the substrate surface,a minimum distance between the heavily doped first and secondsource/drain regions 121, 122 is increased in comparison with a FinFETin which the active area is disposed along the substrate surface and inwhich the current path comprises only a horizontal path. As aconsequence, an electrical field at the source/drain region—channeljunction and, consequently, a leakage current is reduced. Moreover, thehighly doped regions 121, 122 are screened from the gate electrode 852by the spacer portion 86, so that the influence of the electric field ofthe gate electrode on the heavily doped regions is reduced.

FIG. 1B illustrates a cross-section of the transistor in a directionperpendicular to the direction of FIG. 1A. In particular, there is showna section across the fin region 11 of the active area that is a portionof the active area having a narrow width, the fin region beingsurrounded on three sides thereof by the gate electrode. In the finregion 11 the active area has the form of a ridge or a fin. The activearea has a top side 11 a and two lateral sides 11 b, the length of thetop side 11 a being smaller than the length of the lateral sides 11 b.

In FIG. 1B, the plate-like portions 851 of the gate electrode 851 aredisposed along the lateral sides 11 b of the fin, whereas thegroove-like portion 852 of the gate electrode is disposed along the topside 11 a of the fin. The gate electrode 85 is isolated from the finregion 11 by the gate oxide 80. As can be seen from FIG. 1B, the currentpath 15 is in a direction perpendicular to the plane depicted in FIG.1B.

Due to the narrow width of the fin region, the transistor body can befully depleted, so that the off-current of the transistor can beimproved. According to a preferred embodiment of the present invention,the fin region can be locally thinned so that the width of the channelregion is made smaller than the width of the first and secondsource/drain regions. As a consequence, the off-current of thetransistor can be further improved with respect to the known transistorwhile the contact area of the source/drain regions is not decreased. Asa result the contact resistance is not increased.

In the structure illustrated in FIGS. 1A and 1B, the length L_(eff) ofthe channel corresponds to the distance between first and secondsource/drain regions. In addition, the width of the channel correspondsto the width of the region the conductivity of which is controlled bythe gate electrode. Accordingly, the width of the channel corresponds tothe sum of the double of the fin height and the fin width or,differently stated, to the double of the length of the lateral side andthe length of the top side of the ridge. In particular, the channellength L_(eff) can be 30 to 150 nm. Moreover, the height of the fin canbe 20 to 100 nm and the fin width can be 10 to 50 nm.

Accordingly, the transistor of the present invention provides animproved on-current in comparison with known transistors, since thewidth of the channel is increased whereby the resistance is reduced.Moreover, the transistor exhibits a larger slope of the subthresholdcharacteristics and a remarkably reduced body effect. Thereby, theon-current is further increased.

The transistor additionally provides an improved off-current due to itslarger channel length and the larger slope of its subthresholdcharacteristics, in comparison to a known transistor.

In summary, the transistor illustrated in FIGS. 1A and 1B combines animproved on-current with a decreased off-current.

FIG. 1C illustrates a modification of the transistor structureillustrated in FIG. 1A. In FIG. 1C, the first source/drain regioncomprises a heavily doped portion 121″ and a lightly doped region 121′.The lightly doped region 121′ extends to the same depth as the secondsource/drain region 122.

By providing the lightly doped region 121′ between the heavily dopedregion 121″ and the channel 14, the electrical field can be reduced.Accordingly, a junction leakage current can be reduced.

Generally speaking, the leakage current correspond to the currentflowing from the storage capacitor to the second source/drain region orthe silicon body when the gate electrode is not addressed. Sinceespecially the electric fields at the first source/drain region—channeljunction highly influence the leakage current, it is advantageous toreduce the electric field at the first source/drain region—channeljunction. By reducing the leakage current, the retention time, i.e., thetime during which an information is recognizably stored in the memorycell, can be increased.

Accordingly, as the inventors of the present invention found out, anasymmetric arrangement of first and second source/drain regions, inparticular, the arrangement illustrated in FIG. 1C in which the firstsource/drain region 121 comprises a lightly and a heavily doped portionand the lightly doped portion 121′ extends to the same depth as thesecond source/drain region 122 is highly advantageous.

Nevertheless, it lies within the scope of the present invention thatalso the second source/drain region 122 comprises a lightly and aheavily doped portion wherein the lightly doped region is arrangedbetween the heavily doped region and the channel region. In particular,the first and second source/drain regions comprising lightly and heavilydoped portions can be arranged in a symmetric manner.

According to the embodiment illustrated in FIG. 1C, the lower side ofthe lightly doped first source/drain region 121′ is disposed beneath thelower edge of the groove portion 852 of the gate electrode or than thetop side of the fin region. As a consequence, the effective width of thefirst source/drain region can be remarkably increased. Since this widthmainly determines an on-current, the on-current characteristics of thetransistor are further improved.

The heavily doped first source/drain region 121 which will later beconnected with the storage capacitor is shielded from the gate electrodeby the thick spacer 86′. Accordingly, the electric field at thejunction, which is connected with the storage load will be reduced. As aconsequence, the retention time will further be increased.

FIGS. 2A to 2W illustrate a first embodiment of the present invention,in which a memory cell array comprising a transistor of the presentinvention and a trench capacitor are implemented.

FIG. 2A illustrates a plan view on the memory cell array, comprising aplurality of memory cells 100, each memory cell comprising a trenchcapacitor 3 and a transistor 16. A plurality of word lines 8 is arrangedin a first direction, and a plurality of bit lines is arrangedperpendicularly to the word lines 8. Also illustrated in FIG. 2A are thesites I, II, III and IV, which illustrate the directions along which thecross-sectional views illustrated in FIG. 2B, for example, are taken.

More specifically, the cross-sectional view from I to II illustrates across-section perpendicular to a bit line between two adjacent wordlines 8, whereas the cross-sectional view from II to III illustrates across-section perpendicular to the word lines along a bit line 9, andthe cross-sectional view from III to IV illustrates a cross-sectionperpendicular to the bit line 9 along a word line 8.

FIG. 2B illustrates three cross-sectional views which are taken fromsite I to II, from II to III, and III to IV of a memory cell array afterdefining the capacitor trenches. The structure illustrated in FIG. 2Bcan for example be obtained by depositing first, a pad oxide layer (notshown), and a nitride layer 17 as commonly used in the art, on asemiconductor substrate 1, by generally well known methods. Thereafter,the capacitor trenches are photolithographically defined by knownmethods. In particular, openings corresponding to openings in a trenchmask are etched into a hard mask layer (not shown) deposited above thesilicon nitride layer 17. Thereafter, the openings are etched into thesilicon nitride layer 17, the pad oxide layer as well as the siliconsubstrate 1.

In addition, a first capacitor electrode, as well as the capacitordielectric are formed by generally known methods. Thereafter, apolysilicon filling 31 is filled into the capacitor trenches, thepolysilicon fill is recessed and an isolation collar 32 is formed in theupper part of the trench capacitor, in order to suppress a parasitictransistor, which otherwise could be formed at this portion. Theresulting structure is filled with a second polysilicon filling andplanarized by known methods. Thereafter the polysilicon filling isrecessed in a manner similar to the recess 3 etching step which isperformed when forming a buried strap. In particular, the polysiliconfilling is etched 30 nm below the substrate surface 10.

A plan view on the arrangement of capacitor trenches is illustrated inFIG. 2C, in which a plurality of capacitor trenches 3 are arranged in acheckerboard manner. Differently stated, the capacitor trenches arearranged in rows, in which two neighbouring trenches have an equaldistance and the trenches of two adjacent rows are arranged in astaggered manner so that the trenches of a row are disposed at aposition in the middle between two adjacent trenches of the adjacentrows. The size of a memory cell 100 is 2F in a first direction and 4F ina second direction, wherein F denotes the minimal structural sizeobtainable in the corresponding technology.

Next, the active areas are defined photolithograghically and isolationtrenches 2 are etched so as to expose the active areas. It is intendedthat the final width of the active areas is equal to 0,8 F. For example,F can be 100, 80 or 50 nm or assume any desired value. Thereafter, theactive areas are oxidized by a thermal process and the trenches betweenadjacent active areas are filled with a commonly used STI fill. In thepresent example the isolation trenches are filled with a silicon dioxidelayer which also fills the upper part of the capacitor trenches 3 andforms the trench top oxide 34.

After defining the active areas, the arrangement illustrated in FIG. 2Dis obtained, in which reference numeral 12 denotes the active areas. Itis to be noted that in the plan view of FIG. 2D, after etching theisolation trenches, the upper part and the lower part of each of thecapacitor trenches 3 are etched as well.

Next, the semiconductor substrate 1 is shortly dipped in diluted HF, forexample, so as to remove a surface oxide layer (oxide deglaze step). Itis intended that the final step height at the isolation trenches is 0nm. Thereafter, the silicon nitride layer 17 and the pad oxide layer(not shown) are removed by known methods. Thereafter, a sacrificialoxide layer 181 is thermally grown, and the implantation processes inorder to form the doped well regions, which are commonly used in memorycell are performed.

At this point, possibly a blanket light source/drain implant for thedrift region, i.e., the weakly gated portion (not shown) of the currentpath could be performed. These process steps result in the structureillustrated in FIG. 2E.

Next, a silicon nitride layer 182 having a thickness of about 10 nm isdeposited by known methods so as to act as a liner layer in a followingdamascene process. Thereafter, a silicon oxide layer 183 having athickness of about 100 nm is deposited by known methods. Finally, apolysilicon layer 184 having a thickness of about 80 nm, acting as amask layer is deposited by known methods. The resulting structure isillustrated in FIG. 2F.

Using a GC array mask (not shown) having a pitch of 1.4×2.2 F, theopenings for providing the gate electrodes are photolithograghicallydefined by known methods. Thereafter, the polysilicon layer 184 isetched at the defined portions, and thereafter, the silicon oxide layer183 is etched, stopping on the liner layer 182. After removing thesilicon nitride layer 182, an etching step is performed so as to etchsilicon and silicon oxide, until a depth of 40 nm below the siliconsurface 10 is achieved. The resulting structure is illustrated in FIG.2G.

FIG. 2H illustrates a plan view of the resulting structure, in which inthe spaces between two neighbouring trenches in one active area row isdisposed one gate electrode 853.

Thereafter, a further sacrificial oxide layer 181′ is thermally grown onthe exposed silicon portions, in particular, the bottom and the lowerpart of the sidewalls of the trenches defined for the gate electrodes853. Thereafter a silicon nitride spacer layer 86 is deposited andetched so that a final thickness of 0.2 F remains at the sidewalls ofthe defined GC mask openings.

The sacrificial oxide layer 181′ is advantageous since thereby an oxideinterface is provided between the silicon portions in which later thesource/drain regions will be formed and the nitride spacer. As aconsequence, in the transistor to be formed, there will be less surfacestates and, thereby, less leakage current in comparison to a transistorin which the source/drain regions are directly adjacent to the siliconnitride spacer.

The steps described above will result in the structure illustrated inFIG. 2I.

Thereafter, the gate electrode regions are further etched. Inparticular, the bottom part of the sacrificial oxide layer 181′ isetched. In addition, the silicon oxide layer 32 is etched selectively tosilicon and silicon nitride. As a consequence, in the cross-sectionalregion between III and IV, pockets are formed in the silicon oxide layer32. The pockets extend to a depth of 100 to 120 nm below the substratesurface 10.

Thereafter an isotropic etch is performed so as to remove the siliconportions adjacent to the pockets formed in the previous step. Thereby,the fin regions forming part of the active regions are thinned, forexample 10 to 15 nm on each side so as to achieve a final fin width of30 nm. As a consequence, the channel can be fully depleted by applyingan approviate voltage to the gate electrode. Nevertheless, since the finhas only locally be thinned at the portions adjacent to the gateelectrode, the contact area of the source/drain regions has not beendecreased and, consequently, the contact resistance has not beenincreased. In particular, due to the damascene process as described, thethinned active area and the gate electrode are formed in a self-alignedmanner.

The resulting structure is illustrated in FIG. 2J. As can be seen fromthe cross-sectional view between II and III, the defined GC region 854extends to a deeper depth than the side wall spacers 86. In addition, ascan be seen from the cross-sectional view between III and IV, thedefined GC region 854 comprises a central portion and two side wallportions which extend to a deeper depth than the central portion.

After an optional step of forming a sacrificial oxide layer (not shown)for reducing an ion channeling effect, and performing an ionimplantation step for doping the channel region, if needed, the gateoxide layer 80 is grown. Thereafter, a polysilicon layer 185, having athickness of 40 nm, which is in situ doped with phosphorous, isdeposited.

The resulting structure is illustrated in FIG. 2K.

Thereafter, the polysilicon layer 185 is etched to 70 nm below thepolysilicon surface that is illustrated in FIG. 2K, forming the gateelectrode 85. Thereafter, a silicon nitride layer 186 is deposited so asto fill the regions above the gate electrode 85.

The resulting structure is illustrated in FIG. 2L. As is depicted inFIG. 2L, the gate electrode 85 comprises a groove portion 852 and twoplate portions 851.

After removing the silicon nitride layer 186 from the surface, thesilicon oxide layer 183 is removed, and the source/drain-implantsdefining the first and second source/drain regions 121, 122 areperformed. Thereafter, a silicon oxide layer 183 is again deposited andthe GC connect lines are provided. To this end, first, the siliconnitride filling 186 is removed exposing the gate electrode 852.Thereafter an additional Si₃N₄ spacer 87 having a thickness of 0.2 F isdeposited. Accordingly an inner spacer 87, which is thicker than thespacer 86 encloses the GC connect lines. Finally, a doped polysiliconlayer 187 is deposited, so as to fill the openings for the GC connectlines 83.

The resulting structure is illustrated in FIG. 2M. In the next steps,the surface strap regions will be defined. In particular, the strapregions are photolithograghically defined by known methods, so as toopen the polysilicon layer 187 at predetermined portions. Taking thepatterned polysilicon layer 187 is a mask, the silicon oxide 183 isetched selectively with respect to polysilicon and silicon nitride.Thereafter, a silicon nitride liner break through step is performed, andfinally the trench top oxide layer 34 is etched selectively with respectto polysilicon/silicon nitride.

The resulting structure is illustrated in FIG. 2N.

FIG. 2O illustrates a plan view on the resulting memory cell array. Thestrap mask openings 35 are formed between a capacitor trench 3 and adefined GC region 854.

Thereafter, the exposed GC SiN spacer is removed, a pad oxide layer (notshown) is grown and a silicon nitride spacer 37 acting as a strap spaceris deposited and etched. Thereafter, as an optional step, a node implantstep can be performed so as to reduce the contact resistance between theinner capacitor electrode and the surface strap. These steps will resultin the structure illustrated in FIG. 2P.

In order to form a strap connecting the inner capacitor electrode 31with the first source/drain region 121 of the transistor, a TiN liner(not shown) is deposited, followed by a metal layer deposition step.Thereafter, the deposited material is etched so as to form the metalstrap 38. Then, the polysilicon mask layer 187 is removed and a siliconnitride liner 188 having a thickness of 50 nm is deposited so as to fillthe portions above the metal straps 38. Thereafter, the silicon nitrideliner is etched by 60 nm, whereby a smooth surface is provided. Theresulting structure is illustrated in FIG. 2Q.

Thereafter, the steps of forming the word lines 8 are performed. First,by performing a CMP step (chemo-mechanical polishing) the surface isplanarized, polishing the oxide with an over-polish on silicon nitride.Thereafter, a tungsten layer 8 as well as a silicon nitride cap layer 81are deposited. The word lines are photolithograghically defined by knownmethods and etched. After forming the side wall spacers 81 as well asfilling the spaces between adjacent word lines with a BPSG-material 82,the structure illustrated in FIG. 2R is obtained.

FIG. 2S illustrates a similar view which is obtained if instead of aburied strap contact 33 a surface strap 38 for connecting the innercapacitor electrode 31 with the first source/drain region 121 is used.In FIG. 2S, similar components are denoted by the same referencenumerals as in FIG. 2R. As can be seen from FIG. 2S in comparison withFIG. 2R, the gate groove has to be etched much deeper in FIG. 2S than inFIG. 2R in order to provide the same length of the current path.

FIG. 2T illustrates a plan view on the memory cell array comprising thestructures illustrated in FIG. 2R. The word lines 8 are provided so asto connect the gate electrodes 854 of a column with one another.

Next, a BPSG layer 91 acting as a bitline isolator layer is deposited.Then, the openings for providing the bit line contacts 61 arelithographically defined by known methods and etched. Thereafter, theopenings for the bit line contacts 90 are lithographically defined andetched. Then, an implantation step at the bottom of the bit line contactopening is performed so as to improve the contact resistance. Finally,the bit line contact opening is filled and planarized. In addition, theM0 layer is deposited by general known methods, lithographicallypatterned and etched so as to provide the bit lines 9.

Thereafter the usually performed steps of providing the highermetallization layers are performed.

FIG. 2V illustrates a plan view on the memory cell array after formingthe bit line contacts 90. Moreover, FIG. 2W illustrates the plan view onthe memory cell array after patterning the bit lines 9.

In FIG. 2U, in the cross-section between II and III, a transistor 16 isformed between the first and the second source/drain regions 121 and122. The first source/drain region 121 is connected via the surfacestrap 38 and the polysilicon fill 36 with the inner capacitor electrodeof the trench capacitor 3. The conductivity of the channel between thefirst and the second source/drain regions 121 and 122 is controlled bythe gate electrode 85. A current path between the first and the secondsource/drain regions 121 and 122 extends from the surface of the firstsource/drain region 121 to the surface of the second source/drain region122. In the upper part of the current path the electrical potential ofthe gate electrode 85 is shielded by the spacer 86, while in the lowerpart of the current path the conductance is controlled by the gateelectrode. An information stored in the trench capacitor is read by thetransistor and sent to the bit line 9 via the bit line contact 90.

As can be seen from the cross-section between III and IV, the activearea which is enclosed by the gate electrode 85, has a fin region, inwhich the active region has the shape of a fin or a ridge. The gateelectrode surrounds the fin at three sides thereof. In more detail, thegate electrode 85 comprises a groove region 852 as illustrated betweenII and III and two plate-like portions 851 which are adjacent to thesides of the fin.

In the cross-section between III and IV, the fin region which isenclosed by the gate electrode 83 has a more narrow width than theunderlying silicon region.

In FIG. 2S, in which the contact between the first source/drain region121 and the inner capacitor electrode is accomplished by a buried strap33, the current path likewise a vertical component since in this casethe channel is recessed to a deeper depth than in the case of thesurface strap.

FIGS. 3A to 3L illustrate a second embodiment of the present invention,in which a memory cell comprises a stacked capacitor and the transistorwhich is described above with reference to FIGS. 1A and 1B.

FIG. 3A illustrates a layout of the active areas 12 of the memory cellarray. As illustrated in FIG. 3A two active areas 12 in which thetransistor is to be formed are disposed adjacent to each other, and theyshare a common bit line contact 90 which is indicated by broken lines.The stacked capacitors 4 belonging to each of the memory cells 100 arealso indicated by broken lines 4. The segments of the active areas 12are separated from each other by isolation trenches 23.

The sectional views illustrated in FIGS. 3B, 3C, 3F, 3G, and 3J aretaken between the points V and V.

For providing the memory cell array according to the second embodimentof the present invention, first, isolation trenches 23 arephotolithographically defined and etched in the surface 10 of asemiconductor substrate 1. The isolation trenches 23 are filled withsilicon dioxide and, thereafter, the usual implantation steps forproviding the well regions are performed. After a thermal oxidation stepfor providing a sacrificial silicon dioxide layer 181, a silicon nitridelayer 182 having a thickness of about 10 nm is deposited, followed by asilicon dioxide layer 183 having a thickness of 100 nm. Thereafter, apolysilicon mask layer (not shown) having a thickness of about 80 nm isdeposited.

In the next step, the word lines are defined photolithograghically.First a gate electrode mask is used for defining the openings in thepolysilicon mask layer (not shown). The gate electrode mask as used inthe second embodiment contains openings, which have the shape of lines,so that word lines instead of openings, which are separated from eachother, are defined, which has been the case in the first embodiment.

Thereafter, taking the patterned polysilicon mask layer as a mask, theoxide layer 183 is selectively etched until the silicon nitride layer182 is reached. After removing the silicon nitride in the exposedportions, the silicon as well as silicon oxide layer are etched in theexposed portions for about 40 nm below the silicon surface. Thereby, thegroove portion of the gate electrode is defined.

After performing a thermal oxidation step for growing a sacrificialoxide layer (not shown), a silicon nitride spacer 86 is deposited andetched so that a thickness of 0.2 F is achieved. These steps areperformed in a similar manner as described with reference to the firstembodiment as illustrated in FIGS. 2F, 2G, 2J, and 2K. Thereafter, as isalso described with reference to FIG. 2J, the sacrificial oxide layer isremoved and the silicon dioxide layer is removed selectively withrespect to silicon/silicon nitride 100 to 120 nm below the siliconsurface 10. Thereby, the pockets for the plate-like portions of the gateelectrode are defined. Thereafter, an isotropic etch step is performedfor fin thinning, in which on each of the edges 10 to 15 nm is etched,so that a final fin width of 30 nm is achieved.

After performing a thermal oxidation step for growing a gate oxide 80, apolysilicon layer (not shown) which is in situ doped with phosphorushaving a thickness of 40 nm is deposited. The polysilicon material fillsthe groove portion as well as the pockets so as to provide the twoplate-like portions of the gate electrode.

Thereafter, the polysilicon layer is removed from the surface portions,and the silicon dioxide layer 183 is removed from the areas between theword-lines 852. Then, an implantation step for providing thesource/drain regions 121, 122 is performed.

Thereafter, a silicon dioxide layer 183 is filled and a planarizationstep is performed so as to obtain the structure illustrated in FIG. 3B.

Thereafter, the polysilicon material 852 of the wordlines is recessed,and a tungsten layer is deposited so as to fill the spaces above thepolysilicon material 852, planarized and etched below the surface. Then,the spaces above the tungsten lines are filled with a silicon nitridelayer, which is also planarized. The resulting structure is illustratedin FIG. 3C, in which the polysilicon lines 852 are covered by thetungsten lines 8 which are isolated by the silicon nitride layer 81 a.

FIG. 3D illustrates a plan view on the resulting cell array from whichit can be seen that the word lines 8 are perpendicular to the directiondefined by the active areas 12.

In a following step, by using a stripe-like mask 6, contact areas fordefining a contact to the bit line as well as to the stacked capacitorare formed. In particular, as can be seen from FIG. 3E, by selectivelyetching the silicon oxide material at the photolithographically definedportions, openings will be formed at the locations indicated by a “X”.Stated differently, the openings are formed at those areas under theopenings of mask 6, where the word lines are not formed. The crosses areonly indicated along V to V. However, as is clearly to be understood,these openings are also formed at corresponding areas outside V to V.

Thereafter, implantation steps are performed so as to reduce the contactresistance. Finally, the openings 6 are filled by depositing a layer ofa conductive material. The layer is planarized to the nitride cap 81.

The resulting structure is illustrated in FIG. 3F.

As can be seen from FIG. 3F, the conductive material provides thebitline contact assisting structure 90 as well as the assisting contact41 for contacting the stacked capacitor.

In the next step, a silicon dioxide layer 91 is deposited, and,thereafter, the bit line contact openings are lithographically definedby known methods. After forming the corresponding opening in the silicondioxide layer 91, the opening is filled with a conducting material so asto form a bit line contact 61. After a planarizing step, a tungstenlayer 9 and a silicon nitride layer 62 are deposited by known methods.Thereafter, the tungsten layer 9 is photolithograghically patterned soas to form stripes which extend in a direction parallel to the lineconnecting V with V. Thereafter, side wall spacers (not shown) areformed by generally known methods.

The resulting structure is illustrated in FIG. 3G.

FIG. 3H illustrates a plan view on the memory cell array after definingthe bit lines contacts 61. As can be seen, the bit line contacts 61 areformed at the left side of the vertical portions crossing the activeareas 12. One bit line contact 61 is formed for two adjacent memorycells.

FIG. 31 illustrates a plan view on the memory cell array after definingthe bit lines 9. The bit lines 9 are formed perpendicularly to the wordlines 8. The bit lines are disposed above the bit line contacts 61, and,in a plan view, they are disposed in the spaces between neighbouringactive areas 12.

In the next step, the spaces between adjacent bit lines are filled withan oxide layer and the resulting structure is planarized. Thereafter,the capacitor contact structures 42 are photolithograghically defined inthe layer stack by generally known methods. In particular, the openingscorresponding to the capacitor contacts are etched and filled with aconducting material, for example tungsten. In the next step, the stackcapacitor 4 is formed by generally known methods. In particular, anouter capacitor electrode (not shown) is formed and electricallyconnected with a capacitor contact 42, a capacitor dielectric (notshown) is provided and, finally, the inner capacitor electrode isprovided. The resulting structure is illustrated in FIG. 3J. As can beseen, since the first and second source/drain regions are disposedadjacent to the substrate surface 10, an electrical contact to thestacked capacitor can easily be accomplished.

FIG. 3K illustrates a plan view of the memory cell array after formingthe capacitor contact structures 42. In particular, the capacitorcontact mask 43 has stripe-like openings, which are perpendicular to thebit lines 9. Since the bitline material is etched selectively withrespect to the silicon oxide filling the spaces between the bitlines,hole-like openings are formed. The openings opened under the stripes 43are formed above the active areas 12, so as to contact the firstsource/drain regions 121.

FIG. 3L illustrates a plan view on the memory cell after defining thestacked capacitors 4. The stacked capacitors 4 are arranged in acheckerboard pattern, so that the stacked capacitors of two neighbouringrows are arranged in a staggered manner.

FIG. 4A to 4J discloses a third embodiment of the present invention, inwhich a memory cell array comprising the transistor of the presentinvention as described with reference to FIGS. 1B and 1C, and a stackedcapacitor is formed. In particular, according to the third embodiment,the grooves for the gate electrodes are formed at an early process step.

The upper part of FIG. 4A illustrates a plan view on the resultingarray, whereas the lower part of FIG. 4A illustrates a cross-sectionalview. In particular, the left hand side of the cross-sectional viewillustrates the cross-section between points VI and VII as depicted inthe upper part of FIG. 4A, whereas the right hand side of the lower partillustrates the cross-section between VII and VIII.

For implementing the third embodiment of the present invention, first, apad oxide layer (not shown) and a silicon nitride layer 17 are depositedon the surface 10 of a semiconductor substrate 1, in particular, asilicon substrate 1. Thereafter, the active areas 12 of the memory cellare photolithograghically defined by known methods and isolationtrenches 23 are etched in a common manner so as to expose the activeareas 12. The sidewalls of the active areas are oxidized, and theisolation trenches 23 are filled with an isolating material, inparticular, a silicon dioxide layer. The resulting surface isplanarized. The resulting structure is illustrated in the lower part ofFIG. 4A, whereas the upper part of FIG. 4A illustrates a plan view onthe array. As can be gathered from the upper part of FIG. 4A, the lineconnecting VI and VII intersects the active area 12, whereas the lineconnecting VII and VIII intersects the isolation trenches 23 as well asthe active area 12 at the smaller side thereof.

In the next step, the silicon nitride layer 17 as well as the underlyingsilicon dioxide layer are removed by etching. Thereafter, a thermaloxidation step is performed so as to grow a sacrificial oxide layer onthe exposed silicon portions. Thereafter, implantation steps areperformed so as to provide the required doped well regions. As anoptional step, a further implantation step can be performed so as toprovide the lightly n doped first source/drain region 121′.

Thereafter, a hard mask layer or layer stack for defining the groovesfor the gate electrodes is deposited. The hard mask layer may forexample comprise a first layer 71 of polysilicon or carbon and a secondlayer 72 of, for example photo-resist material or carbon. The hard masklayer stack is photolithograghically patterned by using a stripe maskhaving stripes with a width of less than 1 F.

Finally, the hard mask layer stack is etched so as to expose the siliconsubstrate at the groove portions.

As can be seen from FIG. 4B, the isolation material of the isolationtrenches 23 projects with respect to the silicon surface, since in theprevious step of planarizing the surface, the surface of the STIportions has been made coplanar with the surface of the pad nitridelayer 17. As a consequence, after removing the pad nitride layer 17, theisolation material of the isolation trenches 23 projects or protrudeswith respect to the silicon surface 10. During the step of stripping thepad nitride and the pad oxide layer, the material of the isolationtrenches has been etched as well.

As can be gathered from the upper part of FIG. 4B, the portions betweenVII and VIII extend in a groove 7 region, i.e., the region in which thegroove has been etched.

In the next step, an etching step is performed, so as to etch theexposed portions of the isolation material in the isolation trenches 23.Thereafter, the second hard mask layer 72 is removed, and a furtheretching step is performed, so as to etch the groove portions 7 in thesilicon substrate material. In particular, the silicon is etchedapproximately 40 to 150 nm below the substrate surface. The width of thegrooves 73 is 0.5 to 0.7 F.

It is preferable to etch the grooves 73 in such a manner so as to avoidsharp corners at the lower portions of the grooves 73. It isparticularly preferred that these corners be rounded as is indicated bybroken lines in FIG. 4C. As is to be noted from the cross sectionbetween VII and VIII of FIG. 4C, silicon residuals 73′ may be formedbetween the silicon grooves 73 and the adjacent isolation trenches 23.

Thereafter, an etching step of isotropically etching silicon isperformed. This etching step can be a wet etch or a dry etch step, forexample a so-called CDE (chemical downstream etch). Thereby, the groovesformed in the hard mask layer 71 as well as the grooves 73 formed in thepolysilicon material are extended laterally. In particular, the diameterof the grooves is extended by 0,2 F, and, further, silicon residuals 73′which might occur between the groove 73 and the adjacent isolationtrenches 23, as depicted in the cross-sectional part between VII andVIII in FIG. 4C are removed.

The resulting structure is illustrated in FIG. 4D. As can also begathered from the upper part of FIG. 4D, the width of the verticalstripes has been broadened.

The final width of the grooves (CD, “critical dimension”) now amounts to0.9 F.

In a next step, a wet etching of silicon dioxide is performed. By thisisotropic etching step the exposed oxide regions are etched. As aconsequence, the groove in the isolation trench illustrated in the lefthand side of FIG. 4E is widened and deepened, and in the part betweenVII and VIII, pocket structures 74 are formed in the isolation materialof the isolation trenches 23. The size of these pockets 74 is indicatedby broken lines around the grooves 73 illustrated in the cross-sectionalview between VI and VII. In particular, the pocket structures 74 areformed around the fin regions 11. Since this step is performed as a wetetching step, the formation of the pocket structures is accomplished ina self-aligned manner with respect to the groove.

Next, an anisotropic etching step is performed so as to further etchsilicon dioxide. In particular, about 25 nm silicon dioxide are etchedso that the total depth of the pockets 74 amounts to 40 nm below thegroove. As a consequence, as can be seen from the cross section betweenVII and VIII of FIG. 4F, the depth of the fin region 11 amounts toapproximately 40 nm. This is also illustrated in the left hand side ofthis Figure between VI and VII, by reference numeral 74″. The areaetched in the former isotropic etching step is indicated by referencenumeral 74′. The height corresponding to the oxide surface in the righthand side of this Figure is indicated by the broken line 75. As anoptional step, a further silicon etching step can be performed so as tothin the fin region 11. By the selective anisotropic etching step, theetched portions are deepened by they are not broadened.

In a next step, a gate oxide 80 is thermally grown by known methods. InFIG. 4G, the portions 80′ indicated in the cross sectional view betweenVI and VII, indicate the gate oxide portions which are grown above theregions 74′ and would correspond to a cross-section, which is taken inanother plan before or behind the illustrated plane. In addition, apolysilicon layer 187 forming the gate electrode is deposited by knownmethods.

In a next step, the polysilicon material 187 of the gate electrode isisotropically etched to a depth of about 40 nm below the silicon surface10. Thereafter, as an optional step, an angled implantation step so asto provide the lightly n⁻ doped first source/drain region 121′ can beperformed, making use of the fact that the upper part of the grooves 73is exposed.

In a next step, a silicon nitride layer is deposited and etched so as toform a spacer 86. The spacer has a thickness of about 0.2 F. By thisstep, also spacer portions 86′ are formed between VII and VIII.

The resulting structure is illustrated in FIG. 4H.

Thereafter, the exposed portions of the silicon dioxide layer 801 areetched. Then, a polysilicon layer 811 is deposited so as to fill thespaces between the silicon nitride spacers 86. Thereafter, a tungstenlayer 82 as well as a further silicon nitride layer 81 are deposited bygenerally known methods.

The resulting structure is illustrated in FIG. 4I.

In a next step, the word lines will be patterned. Before patterning theword lines, the implantation steps for defining the first and the secondsource/drain regions can be performed so as to form the first and secondsource/drain regions 121, 122. This implantation step could be as wellperformed after defining the word lines.

For patterning the word lines, first the silicon nitride layer 81 willbe etched so as to form stripe-like portions 81 a, thereafter, thetungsten layer 82 will be etched so as to form stripes and finally thepolysilicon layer 811 will be etched so that a gate electrode stack isformed. When etching the polysilicon layer 811, special care has to betaken, that an over-etch step which is usually performed, does notextend to a deep depth since otherwise the resulting transistor will bedegraded. In particular, an over-etching depth of about 20 to 30 nmbelow the silicon surface is considered to be the maximum over-etchingdepth.

As a further alternative, the source/drain regions can also be definedat this point of the process.

The resulting structure is illustrated in FIG. 4J.

Thereafter the usual process steps of finishing the memory cell arraywill be performed. In particular, process steps similar to thosedescribed with respect to FIGS. 3F to FIG. 3L will have to be performed.

When comparing the structures illustrated in FIG. 3F with the structureillustrated in FIG. 4J, it becomes apparent that in FIG. 4J the passingword lines 8 b do not extend to such a deep depth as the correspondingpassing word lines 8 b in FIG. 3F. This is due to the differentmanufacturing process. In particular, according to the third embodiment,first, the groove portion is defined and then, the pockets are etched byan isotropic etching step, whereby the STI filling of the isolationtrenches is not etched at those portions where the gate electrode is notto be formed.

To be more specific, according to the third embodiment, first, siliconis etched selectively with respect to silicon oxide/silicon nitride.Thereafter, silicon oxide is isotropically etched, and, then, siliconoxide is anisotropically etched. Accordingly, it is possible to definethe passing wordlines 8 b near the substrate surface.

As a consequence, the active areas 12 b, which are disposed near thepassing word lines 8 b are not influenced by the passing word lines 8 b.Differently stated, in the active areas 12 b which are disposed near thepassing word lines 8 b, usually a parasitic transistor can be formedwhich acts as a charge pumping device. In particular, the traps existingat the interface between the single crystalline silicon and the silicondioxide layer of the isolation trenches 23 might cause a DC currentwhich disturbs the memory action. Since, as is illustrated in FIG. 4J,the passing word lines 8b do not extend to such a deep depth, thisproblem can be avoided.

As illustrated in FIG. 4J, the first source/drain region comprises aslightly doped portion 121′. As a matter of course, this slightly dopedportion can as well be omitted.

The fourth embodiment of the present invention is directed to a DRAMmemory cell array comprising a capacitor which is implemented as astacked capacitor, and a transistor as is illustrated with reference toFIGS. 1A and 1B. In the memory cell array of the fourth embodiment, thedisturbing influence of the passing word lines is further reduced byarranging the passing word lines on the surface of semiconductorsubstrate 1. To be more specific, according to the fourth embodiment,first, the pockets are defined in the isolation trenches, while theportions of the isolation trenches in which the pockets are not to beformed, are masked. Thereafter, the groove portions are defined. By thesuccession of manufacturing steps, it is possible to arrange the passingwordlines on the substrate surface.

The first step corresponds to the step which is described with referenceto FIG. 4A, and the description thereof therefore is omitted.

After defining the active areas 12 and the isolation trenches 23, thesilicon nitride layer 17 is removed. Thereafter a thermal oxidation stepis performed so as to grow a sacrificial silicon dioxide layer 181.Thereafter, implantation steps are performed so as to provide the dopedwell portions which are usually present in a memory cell, and as anoptional step, the LDD implantation steps can be performed so as todefine the lightly doped portions of the first and second source/drainregions.

Thereafter, a silicon nitride layer 188 is deposited by generally knownmethods. In a next step, a polysilicon layer 51 is deposited bygenerally known methods. On the surface of this polysilicon layer 51, aphotoresist material 52 is deposited, and the photoresist layer 52 isphotolithograghically patterned so as to form openings 53, having alength of 4 F and a width of 1 F. Thereafter, the polysilicon layer 51is etched, so that the openings 53 also penetrate through thepolysilicon layer 51.

The resulting structure is illustrated in FIG. 5A, wherein the lowerportion of FIG. 5A illustrates a cross-sectional view whereas the upperpart of FIG. 5A illustrates a plan view on the memory cell array.

A plurality of active areas 12 are arranged in rows, and neighbouringrows are spaced apart by isolation trenches 23. The segmented activearea portions 12 of a certain row are also isolated from each other byisolation trenches 23. The whole memory cell array is covered by a layerstack comprising the polysilicon layer 51 and the photoresist material52, except for the central portions of the active areas 12. In the upperpart of FIG. 5A the points VI, VII and VIII are illustrated, along whichthe cross-sectional views of the lower part of FIG. 5A are taken. On theway from VI to VII the active area 12 and, in particular, the opening 53is traversed.

Thereafter, similar steps as described with reference to FIG. 4B areperformed. In particular, a carbon hard mask layer 71 is deposited,followed by a layer of photoresist material 72. Thereafter, the groovesfor the gate electrodes 85 are photolithographically defined by commonlyused steps. After patterning the photoresist layer 72, the carbon hardmask layer 71 is etched and grooves 7 are formed.

As can be seen from FIG. 5B, above the active area 12, the grooves 7extend to the surface of the silicon nitride layer 188, whereas abovethe isolation trenches 23 the grooves stop on the polysilicon hard maskportions 51.

In the next step, an etching step of etching silicon dioxide and siliconnitride selectively with respect to polysilicon, silicon and carbon willbe performed. As a consequence, the exposed portions of the silicondioxide layer 181 and the silicon nitride layer 188 will be etched.Accordingly, in the section between VI and VII the silicon substratesurface 10 will be exposed in the groove portions, whereas in thecross-sectional part between VII and VIII pockets 74 will be etchedaround the active area 12. The position of the pockets between sites VIand VII is indicated by a broken line 74′. The duration of the etchingstep will be in accordance with the desired depth of the plate-likeportions of the gate electrode. This is illustrated in FIG. 5C.

In the next step, the groove portion of the gate electrode 852 will bedefined. In particular, silicon is anisotropically etched selectivelywith respect to silicon dioxide so as to define the grooves 73. Thedepth is about 80 nm below the silicon surface 10. By this step,preferably, also the remaining portions of the polysilicon hard masklayer 51 will be removed. As an optional step, an additional isotropicetching step can be performed so as to etch silicon, whereby the finregion 11 will be thinned. The hard mask portions 71 are removed byselectively etching or an ashing step in an O₂ plasma. The resultingstructure is illustrated in FIG. 5D.

As illustrated in the cross-sectional part between VI and VII, grooves73 are formed in the silicon material of the active area 12. As can beseen from the cross-sectional part between VII and VIII, pockets 74 areformed in the silicon dioxide layer. Between the pockets 74, there isthe fin portion, having a smaller width than the underlying siliconmaterial. Above the fin portion 11, the silicon material is alsorecessed so as to form the groove 73. According to the fourth embodimentof the present invention, the grooves 73 can only be etched at thoseportions at which previously the pockets 74 have been defined.Accordingly, the components of the gate electrode are formed in aself-aligned manner.

In a next step, optionally a sacrificial oxide layer can be thermallygrown and subsequently be removed so that holes may be filled. Inaddition, implantation steps can be performed so as to form the firstand second source/drain regions 121 and 122. Thereafter, the gate oxidelayer 80 will be grown by known methods. In a next step, a polysiliconlayer 187 is deposited. The resulting structure is illustrated in FIG.5E.

Thereafter, the polysilicon layer 187 is etched, so as to form a recesswhich extends to a depth of about 40 nm below the silicon surface 10. Asan optional step, an angled array implant step (LDD implant) can beperformed in order to form a slightly n⁻ doped portion of thesource/drain region which is self-aligned to the spacer depth.

The resulting structure is illustrated in FIG. 5F.

In the next step the inner spacer 86 will be formed. In contrast to theembodiments previously described, the spacer used at this process stepcan be made of silicon dioxide. The use of silicon dioxide isadvantageous since SiO₂ has screening properties which are improved withrespect of the screening properties of Si₃N₄. As a consequence,cross-talking between the word lines and other adjacent conductive partsin the active area 12 will be reduced.

Since silicon nitride is easier to handle, silicon nitride is usuallyused as the spacer material. According to the fourth embodiment of thepresent invention, due to the improved manufacturing process, SiO₂ canbe used instead of Si₃N₄. The spacer 86 has a width of 0.2 to 0.3 F,which depends on the width of the resulting transistor. The resultingstructure is illustrated in FIG. 5G.

Thereafter, a further polysilicon layer 811 is deposited, as illustratedin FIG. 5H.

Next, the word lines will be defined in the manner which is similar tothe manner described with respect to FIG. 4I. First, a tungsten layer 82as well as a silicon nitride cap layer 81 are deposited by known methods(see FIG. 51).

Thereafter, the layer stack is photolithograghically patterned, so as toform single word lines 82 having a silicon nitride cap 81 a on top. Thisis illustrated in FIG. 5J.

In the next step, a silicon nitride layer will deposited and etched soas to form a spacer 81 b. Thereafter, the HDD implantation step so as toform the first and second source/drain regions 121 and 122 can beperformed. Thereafter, the usual steps for completing the memory cellarray will be performed. In particular, the steps described with respectto FIGS. 3F to FIG. 3L will be performed so as to provide the bit lines,the bit line contacts, the stacked capacitors as well as the connectorsbetween stack capacitor and first source/drain regions 121.

When comparing the transistor structure illustrated in FIG. 5K with thetransistor structure illustrated in FIG. 4J, it can be gathered that thepassing word lines 5 b are disposed on the substrate surface and,consequently, further screened from the neighbouring active area 12. Inparticular, the passing word line 8 b does not extend into the siliconsubstrate 1, so that the influence of the passing word line 8 b on theneighbouring active area 12 b can be minimized.

A further difference between the structure illustrated in FIG. 5K andthe structure illustrated in FIG. 4J is that the spacer 86 is made ofsilicon dioxide in FIG. 5K whereas it is made from silicon nitride inFIG. 4J. Nevertheless, according to the fourth embodiment of theinvention, the spacer 86 could as well be made of silicon nitride.

Although the first source/drain region 121 is illustrated as only oneregion in FIG. 5K, it is clearly to be understood that the firstsource/drain region 121 may comprise a lightly doped portion 121′ as isalso illustrated in FIG. 4J, and a heavily doped portion 121. Inaddition, as is also illustrated in FIG. 4J, the second source/drainregion 122 can extend to a deeper depth.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat a variety of alternate and/or equivalent implementations may besubstituted for the specific embodiments illustrated and describedwithout departing from the scope of the present invention. Thisapplication is intended to cover any adaptations or variations of thespecific embodiments discussed herein. Therefore, it is intended thatthis invention be limited only by the claims and the equivalentsthereof.

1. A transistor, suitable for use in a DRAM cell, said transistor beingformed at least partially in a semiconductor substrate, comprising: afirst source/drain region; a first contact region which is adapted toconnect said first source/drain region with an electrode of a storagecapacitor; a second source/drain region; a second contact region whichis adapted to connect said second source/drain region with a bitline; achannel region connecting said first and second source/drain regions,said channel region being disposed in said semiconductor substrate, afirst direction being defined by a line connecting said first and secondsource/drain regions; and a gate electrode disposed along said channelregion and being electrically isolated from said channel region by agate isolating layer, said gate electrode controlling an electricalcurrent flowing between said first and second source/drain regions,wherein said channel region comprises a fin-region in which said channelregion has the shape of a ridge and in which the gate electrode isdisposed at three sides of the channel region, wherein a current pathconnecting said first and second contact regions comprises a firstvertical region in which the direction of said current has a componentin a first vertical direction, a horizontal region in which thedirection of said current has a horizontal component, and a secondvertical region in which the direction of said current has a componentin a second vertical direction, said first vertical direction beingopposed to said second vertical direction.
 2. The transistor accordingto claim 1, further comprising a spacer made from an isolating material,said spacer being arranged at an interface between said gate electrodeand said first and second vertical regions of said current path andhaving a thickness larger than that of said gate isolating layer.
 3. Thetransistor according to claim 1, wherein said first and secondsource/drain regions are arranged within said first and second verticalregions, respectively.
 4. The transistor according to claim 1, whereinthe width of said channel region is smaller than the width of said firstor second source/drain regions, the width being measured in a directionperpendicular to said first direction and parallel to a surface of saidsemiconductor substrate.
 5. A transistor, suitable for use in a DRAMcell, said transistor being formed at least partially in a semiconductorsubstrate, comprising: a first source/drain region which is adapted tobe connected with an electrode of a storage capacitor; a secondsource/drain region which is adapted to be connected with a bitline; achannel region connecting said first and second source/drain regions,said channel region being disposed in said semiconductor substrate, afirst direction being defined by a line connecting said first and secondsource/drain regions; and a gate electrode disposed along said channelregion and being electrically isolated from said channel region by agate isolating layer, said gate electrode controlling an electricalcurrent flowing between said first and second source/drain regions,wherein said channel region comprises a fin-region in which the channelhas the shape of a ridge, said ridge comprising a top side and twolateral sides in a cross section perpendicular to said first direction,wherein said top side is disposed beneath a surface of saidsemiconductor substrate and said gate electrode is disposed along saidtop side and said two lateral sides.
 6. The transistor according toclaim 5, wherein the distance between said top side and said substratesurface, measured in a direction perpendicular to said substratesurface, is 10 to 200 nm.
 7. The transistor according to claim 5,further comprising a spacer made from an isolating material, said spacerbeing arranged at an interface between said gate electrode and saidfirst and second source/drain regions.
 8. The transistor according toclaim 5, wherein said first source/drain region comprises a heavilydoped and a lightly doped region, said lightly doped region beingdisposed between said heavily doped region and said channel region. 9.The transistor according to claim 8, wherein said lightly doped regionextends to a depth beneath said top side of said fin region.
 10. Thetransistor according to claim 9, further comprising a spacer made froman isolating material, said spacer being arranged at an interfacebetween said gate electrode and said first and second source/drainregions.
 11. The transistor according to claim 10, wherein said heavilydoped region is disposed above said lightly doped region and said spacerextends to a depth corresponding to the depth of said heavily dopedregion.
 12. The transistor according to claim 5, wherein said firstsource/drain region extends to the same depth as the second source/drainregion.
 13. The transistor according to claim 7, wherein the isolatingmaterial of said spacer is selected from the group consisting of silicondioxide and silicon nitride.
 14. The transistor according to claim 5,wherein the width of said channel region is smaller than the width ofsaid first or second source/drain regions, wherein the width is measuredin a direction perpendicular to said first direction and parallel tosaid surface of said semiconductor substrate.
 15. A memory cell arraycomprising a plurality of memory cells, a plurality of bitlines whichare arranged in a first direction and a plurality of wordlines which arearranged in a second direction intersecting said first direction, eachof said memory cells comprising: a storage capacitor; a transistor whichis at least partially formed in a semiconductor substrate saidtransistor comprising; a first source/drain region which is connectedwith an electrode of said storage capacitor; a second source/drainregion; a channel region connecting said first and second doped regions,said channel region being disposed in said semiconductor substrate; anda gate electrode disposed along said channel region and beingelectrically isolated from said channel region, said gate electrodecontrolling an electrical current flowing between said first and secondsource/drain regions, wherein said channel region comprises a fin-regionin which the channel assumes the shape of a ridge, said ridge comprisinga top side and two lateral sides in a cross section perpendicular to aline connecting said first and second source/drain regions, wherein saidtop side is disposed beneath a surface of said semiconductor substrateand said gate electrode is disposed along said top side and said twolateral sides, wherein each of said wordlines is electrically connectedwith a plurality of gate electrodes, and wherein said secondsource/drain region of each of said transistors is connected with one ofsaid bitlines via a bitline contact.
 16. The memory cell array accordingto claim 15, wherein said storage capacitor is a trench capacitor. 17.The memory cell array according to claim 15, wherein said storagecapacitor is a stacked capacitor.
 18. The memory cell array according toclaim 15, wherein said memory cells are disposed in rows and columns,respectively, and said storage capacitors and said transistors arearranged in a checkerboard pattern so that said transistors are relatedto first sites and said storage capacitors are related to second sites,one of said first sites being disposed between two of said second sitesand vice versa.
 19. The memory cell array according to claim 15, whereinsaid memory cells are disposed in rows and columns, respectively, andsaid storage capacitors and said transistors are arranged in pairs sothat two storage capacitors are arranged adjacent to each other and twotransistors are adjacent to each other and two neighbouring memory cellsshare a common bitline contact.
 20. The memory cell array according toclaim 15, wherein each of said wordlines comprises a plurality ofpassing wordline portions in which the wordline is not connected with agate electrode, said passing wordline portions being disposed at a depthof said substrate which is smaller than a depth of said gate electrodes.21. The memory cell array according to claim 15, wherein each of saidwordlines comprises a plurality of passing wordline portions in whichthe wordline is not connected with a gate electrode, said passingwordline portions being disposed on the substrate surface. 22-29.(canceled)
 30. A transistor comprising: a first source/drain region; asecond source/drain region; a channel region between the first andsecond source/drain regions; and a gate electrode, wherein the channelregion comprises a fin-region in the shape of a ridge, the ridgecomprising a top side and two lateral sides, the top side disposedbeneath a surface of a semiconductor substrate and the gate electrodedisposed along the top side and the two lateral sides.
 31. Thetransistor of claim 30, further comprising: a spacer between the gateelectrode and the first and second source/drain regions.
 32. Thetransistor of claim 30, wherein the first source/drain region comprisesa heavily doped and a lightly doped region, the lightly doped regionbetween the heavily doped region and the channel region.
 33. Thetransistor of claim 32, wherein the lightly doped region extends belowthe top side of the fin-region.
 34. The transistor of claim 33, furthercomprising: a spacer between the gate electrode and the first and secondsource/drain regions.
 35. The transistor of claim 34, wherein theheavily doped region is above the lightly doped region and the spacerextends to a depth corresponding to a depth of the heavily doped region.36. The transistor of claim 30, wherein the first source/drain regionextends to a same depth as the second source/drain region.